#ifndef ASIC_REG_GAUDI2_REGS_H_
#define ASIC_REG_GAUDI2_REGS_H_
#include "gaudi2_blocks_linux_driver.h"
#include "psoc_reset_conf_regs.h"
#include "psoc_global_conf_regs.h"
#include "cpu_if_regs.h"
#include "pcie_aux_regs.h"
#include "pcie_dbi_regs.h"
#include "pcie_wrap_regs.h"
#include "pmmu_hbw_stlb_regs.h"
#include "psoc_timestamp_regs.h"
#include "psoc_etr_regs.h"
#include "xbar_edge_0_regs.h"
#include "xbar_mid_0_regs.h"
#include "arc_farm_kdma_regs.h"
#include "arc_farm_kdma_ctx_regs.h"
#include "arc_farm_kdma_kdma_cgm_regs.h"
#include "arc_farm_arc0_aux_regs.h"
#include "arc_farm_arc0_acp_eng_regs.h"
#include "arc_farm_kdma_ctx_axuser_regs.h"
#include "arc_farm_arc0_dup_eng_axuser_regs.h"
#include "arc_farm_arc0_dup_eng_regs.h"
#include "dcore0_sync_mngr_objs_regs.h"
#include "dcore0_sync_mngr_glbl_regs.h"
#include "dcore0_sync_mngr_mstr_if_axuser_regs.h"
#include "dcore1_sync_mngr_glbl_regs.h"
#include "pdma0_qm_arc_aux_regs.h"
#include "pdma0_core_ctx_regs.h"
#include "pdma0_core_regs.h"
#include "pdma0_qm_axuser_secured_regs.h"
#include "pdma0_qm_regs.h"
#include "pdma0_qm_cgm_regs.h"
#include "pdma0_core_ctx_axuser_regs.h"
#include "pdma1_core_ctx_axuser_regs.h"
#include "pdma0_qm_axuser_nonsecured_regs.h"
#include "pdma1_qm_axuser_nonsecured_regs.h"
#include "dcore0_tpc0_qm_regs.h"
#include "dcore0_tpc0_qm_cgm_regs.h"
#include "dcore0_tpc0_qm_axuser_nonsecured_regs.h"
#include "dcore0_tpc0_qm_arc_aux_regs.h"
#include "dcore0_tpc0_cfg_regs.h"
#include "dcore0_tpc0_cfg_qm_regs.h"
#include "dcore0_tpc0_cfg_axuser_regs.h"
#include "dcore0_tpc0_cfg_qm_sync_object_regs.h"
#include "dcore0_tpc0_cfg_kernel_regs.h"
#include "dcore0_tpc0_cfg_kernel_tensor_0_regs.h"
#include "dcore0_tpc0_cfg_qm_tensor_0_regs.h"
#include "dcore0_tpc0_cfg_special_regs.h"
#include "dcore0_tpc0_eml_funnel_regs.h"
#include "dcore0_tpc0_eml_etf_regs.h"
#include "dcore0_tpc0_eml_stm_regs.h"
#include "dcore0_tpc0_eml_busmon_0_regs.h"
#include "dcore0_tpc0_eml_spmu_regs.h"
#include "pmmu_pif_regs.h"
#include "dcore0_edma0_qm_cgm_regs.h"
#include "dcore0_edma0_core_regs.h"
#include "dcore0_edma0_qm_regs.h"
#include "dcore0_edma0_qm_arc_aux_regs.h"
#include "dcore0_edma0_core_ctx_regs.h"
#include "dcore0_edma0_core_ctx_axuser_regs.h"
#include "dcore0_edma0_qm_axuser_nonsecured_regs.h"
#include "dcore0_edma1_core_ctx_axuser_regs.h"
#include "dcore0_edma1_qm_axuser_nonsecured_regs.h"
#include "dcore0_hmmu0_stlb_regs.h"
#include "dcore0_hmmu0_mmu_regs.h"
#include "rot0_qm_regs.h"
#include "rot0_qm_cgm_regs.h"
#include "rot0_qm_arc_aux_regs.h"
#include "rot0_regs.h"
#include "rot0_desc_regs.h"
#include "rot0_qm_axuser_nonsecured_regs.h"
#include "dcore0_rtr0_mstr_if_rr_prvt_hbw_regs.h"
#include "dcore0_rtr0_mstr_if_rr_prvt_lbw_regs.h"
#include "dcore0_rtr0_mstr_if_rr_shrd_hbw_regs.h"
#include "dcore0_rtr0_mstr_if_rr_shrd_lbw_regs.h"
#include "dcore0_rtr0_ctrl_regs.h"
#include "dcore0_dec0_cmd_regs.h"
#include "dcore0_vdec0_brdg_ctrl_regs.h"
#include "dcore0_vdec0_brdg_ctrl_axuser_dec_regs.h"
#include "dcore0_vdec0_brdg_ctrl_axuser_msix_abnrm_regs.h"
#include "dcore0_vdec0_brdg_ctrl_axuser_msix_l2c_regs.h"
#include "dcore0_vdec0_brdg_ctrl_axuser_msix_nrm_regs.h"
#include "dcore0_vdec0_brdg_ctrl_axuser_msix_vcd_regs.h"
#include "dcore0_vdec0_ctrl_special_regs.h"
#include "pcie_vdec0_brdg_ctrl_axuser_dec_regs.h"
#include "pcie_vdec0_brdg_ctrl_axuser_msix_abnrm_regs.h"
#include "pcie_vdec0_brdg_ctrl_axuser_msix_l2c_regs.h"
#include "pcie_vdec0_brdg_ctrl_axuser_msix_nrm_regs.h"
#include "pcie_vdec0_brdg_ctrl_axuser_msix_vcd_regs.h"
#include "pcie_dec0_cmd_regs.h"
#include "pcie_vdec0_brdg_ctrl_regs.h"
#include "pcie_vdec0_ctrl_special_regs.h"
#include "dcore0_mme_qm_regs.h"
#include "dcore0_mme_qm_arc_aux_regs.h"
#include "dcore0_mme_qm_axuser_secured_regs.h"
#include "dcore0_mme_qm_cgm_regs.h"
#include "dcore0_mme_qm_arc_acp_eng_regs.h"
#include "dcore0_mme_qm_axuser_nonsecured_regs.h"
#include "dcore0_mme_qm_arc_dup_eng_regs.h"
#include "dcore0_mme_qm_arc_dup_eng_axuser_regs.h"
#include "dcore0_mme_sbte0_mstr_if_axuser_regs.h"
#include "dcore0_mme_wb0_mstr_if_axuser_regs.h"
#include "dcore0_mme_acc_regs.h"
#include "dcore0_mme_ctrl_lo_regs.h"
#include "dcore1_mme_ctrl_lo_regs.h"
#include "dcore3_mme_ctrl_lo_regs.h"
#include "dcore0_mme_ctrl_lo_mme_axuser_regs.h"
#include "dcore0_mme_ctrl_lo_arch_agu_cout0_master_regs.h"
#include "dcore0_mme_ctrl_lo_arch_agu_cout0_slave_regs.h"
#include "dcore0_mme_ctrl_lo_arch_agu_cout1_master_regs.h"
#include "dcore0_mme_ctrl_lo_arch_agu_cout1_slave_regs.h"
#include "dcore0_mme_ctrl_lo_arch_agu_in0_master_regs.h"
#include "dcore0_mme_ctrl_lo_arch_agu_in0_slave_regs.h"
#include "dcore0_mme_ctrl_lo_arch_agu_in1_master_regs.h"
#include "dcore0_mme_ctrl_lo_arch_agu_in1_slave_regs.h"
#include "dcore0_mme_ctrl_lo_arch_agu_in2_master_regs.h"
#include "dcore0_mme_ctrl_lo_arch_agu_in2_slave_regs.h"
#include "dcore0_mme_ctrl_lo_arch_agu_in3_master_regs.h"
#include "dcore0_mme_ctrl_lo_arch_agu_in3_slave_regs.h"
#include "dcore0_mme_ctrl_lo_arch_agu_in4_master_regs.h"
#include "dcore0_mme_ctrl_lo_arch_agu_in4_slave_regs.h"
#include "dcore0_mme_ctrl_lo_arch_base_addr_regs.h"
#include "dcore0_mme_ctrl_lo_arch_non_tensor_end_regs.h"
#include "dcore0_mme_ctrl_lo_arch_non_tensor_start_regs.h"
#include "dcore0_mme_ctrl_lo_arch_tensor_a_regs.h"
#include "dcore0_mme_ctrl_lo_arch_tensor_b_regs.h"
#include "dcore0_mme_ctrl_lo_arch_tensor_cout_regs.h"
#include "pcie_wrap_special_regs.h"
#include "pdma0_qm_masks.h"
#include "pdma0_core_masks.h"
#include "pdma0_core_special_masks.h"
#include "psoc_global_conf_masks.h"
#include "psoc_reset_conf_masks.h"
#include "arc_farm_kdma_masks.h"
#include "arc_farm_kdma_ctx_masks.h"
#include "arc_farm_arc0_aux_masks.h"
#include "arc_farm_kdma_ctx_axuser_masks.h"
#include "dcore0_sync_mngr_objs_masks.h"
#include "dcore0_sync_mngr_glbl_masks.h"
#include "dcore0_sync_mngr_mstr_if_axuser_masks.h"
#include "dcore0_tpc0_cfg_masks.h"
#include "dcore0_mme_ctrl_lo_masks.h"
#include "dcore0_mme_sbte0_masks.h"
#include "dcore0_edma0_qm_masks.h"
#include "dcore0_edma0_core_masks.h"
#include "dcore0_hmmu0_stlb_masks.h"
#include "dcore0_hmmu0_mmu_masks.h"
#include "dcore0_dec0_cmd_masks.h"
#include "dcore0_vdec0_brdg_ctrl_masks.h"
#include "pcie_dec0_cmd_masks.h"
#include "pcie_vdec0_brdg_ctrl_masks.h"
#include "rot0_masks.h"
#include "pmmu_hbw_stlb_masks.h"
#include "psoc_etr_masks.h"
#define mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR …
#define mmDCORE0_TPC0_EML_CFG_DBG_CNT …
#define SM_OBJS_PROT_BITS_OFFS …
#define DCORE_OFFSET …
#define DCORE_EDMA_OFFSET …
#define DCORE_TPC_OFFSET …
#define DCORE_DEC_OFFSET …
#define DCORE_HMMU_OFFSET …
#define NIC_QM_OFFSET …
#define PDMA_OFFSET …
#define ROT_OFFSET …
#define TPC_CFG_BASE_ADDRESS_HIGH_OFFSET …
#define TPC_CFG_SM_BASE_ADDRESS_HIGH_OFFSET …
#define TPC_CFG_STALL_OFFSET …
#define TPC_CFG_STALL_ON_ERR_OFFSET …
#define TPC_CFG_TPC_INTR_MASK_OFFSET …
#define TPC_CFG_MSS_CONFIG_OFFSET …
#define TPC_EML_CFG_DBG_CNT_OFFSET …
#define EDMA_CORE_CFG_STALL_OFFSET …
#define MME_CTRL_LO_QM_STALL_OFFSET …
#define MME_ACC_INTR_MASK_OFFSET …
#define MME_ACC_WR_AXI_AGG_COUT0_OFFSET …
#define MME_ACC_WR_AXI_AGG_COUT1_OFFSET …
#define MME_ACC_AP_LFSR_POLY_OFFSET …
#define MME_ACC_AP_LFSR_SEED_SEL_OFFSET …
#define MME_ACC_AP_LFSR_SEED_WDATA_OFFSET …
#define DMA_CORE_CFG_0_OFFSET …
#define DMA_CORE_CFG_1_OFFSET …
#define DMA_CORE_PROT_OFFSET …
#define DMA_CORE_ERRMSG_ADDR_LO_OFFSET …
#define DMA_CORE_ERRMSG_ADDR_HI_OFFSET …
#define DMA_CORE_ERRMSG_WDATA_OFFSET …
#define QM_PQ_BASE_LO_0_OFFSET …
#define QM_PQ_BASE_HI_0_OFFSET …
#define QM_PQ_SIZE_0_OFFSET …
#define QM_PQ_PI_0_OFFSET …
#define QM_PQ_CI_0_OFFSET …
#define QM_CP_FENCE0_CNT_0_OFFSET …
#define QM_CP_MSG_BASE0_ADDR_LO_0_OFFSET …
#define QM_CP_MSG_BASE0_ADDR_HI_0_OFFSET …
#define QM_CP_MSG_BASE1_ADDR_LO_0_OFFSET …
#define QM_CP_MSG_BASE1_ADDR_HI_0_OFFSET …
#define QM_CP_CFG_OFFSET …
#define QM_PQC_HBW_BASE_LO_0_OFFSET …
#define QM_PQC_HBW_BASE_HI_0_OFFSET …
#define QM_PQC_SIZE_0_OFFSET …
#define QM_PQC_PI_0_OFFSET …
#define QM_PQC_LBW_WDATA_0_OFFSET …
#define QM_PQC_LBW_BASE_LO_0_OFFSET …
#define QM_PQC_LBW_BASE_HI_0_OFFSET …
#define QM_GLBL_ERR_ADDR_LO_OFFSET …
#define QM_PQC_CFG_OFFSET …
#define QM_ARB_CFG_0_OFFSET …
#define QM_GLBL_CFG0_OFFSET …
#define QM_GLBL_CFG1_OFFSET …
#define QM_GLBL_CFG2_OFFSET …
#define QM_GLBL_PROT_OFFSET …
#define QM_GLBL_ERR_CFG_OFFSET …
#define QM_GLBL_ERR_CFG1_OFFSET …
#define QM_GLBL_ERR_ADDR_HI_OFFSET …
#define QM_GLBL_ERR_WDATA_OFFSET …
#define QM_ARB_ERR_MSG_EN_OFFSET …
#define QM_ARB_SLV_CHOISE_WDT_OFFSET …
#define QM_FENCE2_OFFSET …
#define QM_SEI_STATUS_OFFSET …
#define QM_CQ_TSIZE_STS_4_OFFSET …
#define QM_CQ_PTR_LO_STS_4_OFFSET …
#define QM_CQ_PTR_HI_STS_4_OFFSET …
#define QM_ARC_CQ_TSIZE_STS_OFFSET …
#define QM_ARC_CQ_PTR_LO_STS_OFFSET …
#define QM_ARC_CQ_PTR_HI_STS_OFFSET …
#define QM_CP_STS_4_OFFSET …
#define QM_CP_CURRENT_INST_LO_4_OFFSET …
#define QM_CP_CURRENT_INST_HI_4_OFFSET …
#define SFT_OFFSET …
#define SFT_IF_RTR_OFFSET …
#define ARC_HALT_REQ_OFFSET …
#define ARC_HALT_ACK_OFFSET …
#define ARC_REGION_CFG_OFFSET(region) …
#define ARC_DCCM_UPPER_EN_OFFSET …
#define PCIE_VDEC_OFFSET …
#define DCORE_MME_SBTE_OFFSET …
#define DCORE_MME_WB_OFFSET …
#define DCORE_RTR_OFFSET …
#define DCORE_VDEC_OFFSET …
#define MMU_OFFSET(REG) …
#define MMU_BYPASS_OFFSET …
#define MMU_SPI_SEI_MASK_OFFSET …
#define MMU_SPI_SEI_CAUSE_OFFSET …
#define MMU_ENABLE_OFFSET …
#define MMU_DDR_RANGE_REG_ENABLE …
#define MMU_RR_SEC_MIN_63_32_0_OFFSET …
#define MMU_RR_SEC_MIN_31_0_0_OFFSET …
#define MMU_RR_SEC_MAX_63_32_0_OFFSET …
#define MMU_RR_SEC_MAX_31_0_0_OFFSET …
#define MMU_RR_PRIV_MIN_63_32_0_OFFSET …
#define MMU_RR_PRIV_MIN_31_0_0_OFFSET …
#define MMU_RR_PRIV_MAX_63_32_0_OFFSET …
#define MMU_RR_PRIV_MAX_31_0_0_OFFSET …
#define MMU_INTERRUPT_CLR_OFFSET …
#define STLB_OFFSET(REG) …
#define STLB_BUSY_OFFSET …
#define STLB_ASID_OFFSET …
#define STLB_HOP0_PA43_12_OFFSET …
#define STLB_HOP0_PA63_44_OFFSET …
#define STLB_HOP_CONFIGURATION_OFFSET …
#define STLB_INV_ALL_START_OFFSET …
#define STLB_SRAM_INIT_OFFSET …
#define STLB_SET_THRESHOLD_HOP3_OFFSET …
#define STLB_SET_THRESHOLD_HOP2_OFFSET …
#define STLB_SET_THRESHOLD_HOP1_OFFSET …
#define STLB_SET_THRESHOLD_HOP0_OFFSET …
#define STLB_RANGE_INV_START_LSB_OFFSET …
#define STLB_RANGE_INV_START_MSB_OFFSET …
#define STLB_RANGE_INV_END_LSB_OFFSET …
#define STLB_RANGE_INV_END_MSB_OFFSET …
#define STLB_LL_LOOKUP_MASK_63_32_OFFSET …
#define STLB_RANGE_CACHE_INVALIDATION_OFFSET …
#define RTR_MSTR_IF_OFFSET …
#define RTR_LBW_MSTR_IF_OFFSET …
#define DEC_RAZWI_HBW_AW_ADDR_HI …
#define DEC_RAZWI_HBW_AW_ADDR_LO …
#define DEC_RAZWI_HBW_AW_SET …
#define DEC_RAZWI_HBW_AR_ADDR_HI …
#define DEC_RAZWI_HBW_AR_ADDR_LO …
#define DEC_RAZWI_HBW_AR_SET …
#define DEC_RAZWI_LBW_AW_ADDR …
#define DEC_RAZWI_LBW_AW_SET …
#define DEC_RAZWI_LBW_AR_ADDR …
#define DEC_RAZWI_LBW_AR_SET …
#define RR_SHRD_HBW_AW_RAZWI_HI …
#define RR_SHRD_HBW_AW_RAZWI_LO …
#define RR_SHRD_HBW_AR_RAZWI_HI …
#define RR_SHRD_HBW_AR_RAZWI_LO …
#define RR_SHRD_HBW_AW_RAZWI_XY …
#define RR_SHRD_HBW_AR_RAZWI_XY …
#define RR_SHRD_HBW_AW_RAZWI_HAPPENED …
#define RR_SHRD_HBW_AR_RAZWI_HAPPENED …
#define RR_SHRD_LBW_AW_RAZWI …
#define RR_SHRD_LBW_AR_RAZWI …
#define RR_SHRD_LBW_AW_RAZWI_XY …
#define RR_SHRD_LBW_AR_RAZWI_XY …
#define RR_SHRD_LBW_AW_RAZWI_HAPPENED …
#define RR_SHRD_LBW_AR_RAZWI_HAPPENED …
#define BRDG_CTRL_BLOCK_OFFSET …
#define SPECIAL_BLOCK_OFFSET …
#define SFT_DCORE_OFFSET …
#define SFT_IF_OFFSET …
#define BRDG_CTRL_NRM_MSIX_LBW_AWADDR …
#define BRDG_CTRL_NRM_MSIX_LBW_WDATA …
#define BRDG_CTRL_ABNRM_MSIX_LBW_AWADDR …
#define BRDG_CTRL_ABNRM_MSIX_LBW_WDATA …
#define RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_LO_0_OFFSET …
#define RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_HI_0_OFFSET …
#define RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_LO_0_OFFSET …
#define RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_HI_0_OFFSET …
#define RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_LO_0_OFFSET …
#define RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_HI_0_OFFSET …
#define RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_LO_0_OFFSET …
#define RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_HI_0_OFFSET …
#define RR_SHRD_HBW_SEC_RANGE_MIN_HI_0_OFFSET …
#define RR_SHRD_HBW_SEC_RANGE_MIN_LO_0_OFFSET …
#define RR_SHRD_HBW_SEC_RANGE_MAX_HI_0_OFFSET …
#define RR_SHRD_HBW_SEC_RANGE_MAX_LO_0_OFFSET …
#define RR_SHRD_HBW_PRIV_RANGE_MIN_HI_0_OFFSET …
#define RR_SHRD_HBW_PRIV_RANGE_MIN_LO_0_OFFSET …
#define RR_SHRD_HBW_PRIV_RANGE_MAX_HI_0_OFFSET …
#define RR_SHRD_HBW_PRIV_RANGE_MAX_LO_0_OFFSET …
#define RR_LBW_SEC_RANGE_MIN_SHORT_0_OFFSET …
#define RR_LBW_SEC_RANGE_MAX_SHORT_0_OFFSET …
#define RR_LBW_PRIV_RANGE_MIN_SHORT_0_OFFSET …
#define RR_LBW_PRIV_RANGE_MAX_SHORT_0_OFFSET …
#define RR_LBW_SEC_RANGE_MIN_0_OFFSET …
#define RR_LBW_SEC_RANGE_MAX_0_OFFSET …
#define RR_LBW_PRIV_RANGE_MIN_0_OFFSET …
#define RR_LBW_PRIV_RANGE_MAX_0_OFFSET …
#define ARC_AUX_DCCM_QUEUE_PUSH_REG_0_OFFSET …
#define MMU_STATIC_MULTI_PAGE_SIZE_OFFSET …
#define HBM_MC_SPI_TEMP_PIN_CHG_MASK …
#define HBM_MC_SPI_THR_ENG_MASK …
#define HBM_MC_SPI_THR_DIS_ENG_MASK …
#define HBM_MC_SPI_IEEE1500_COMP_MASK …
#define HBM_MC_SPI_IEEE1500_PAUSED_MASK …
#define ARC_FARM_OFFSET …
#include "nic0_qpc0_regs.h"
#include "nic0_qm0_regs.h"
#include "nic0_qm_arc_aux0_regs.h"
#include "nic0_qm0_cgm_regs.h"
#include "nic0_umr0_0_completion_queue_ci_1_regs.h"
#include "nic0_umr0_0_unsecure_doorbell0_regs.h"
#define NIC_OFFSET …
#define NIC_UMR_OFFSET …
#endif