//===-- GCNPreRAOptimizations.cpp -----------------------------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // /// \file /// This pass combines split register tuple initialization into a single pseudo: /// /// undef %0.sub1:sreg_64 = S_MOV_B32 1 /// %0.sub0:sreg_64 = S_MOV_B32 2 /// => /// %0:sreg_64 = S_MOV_B64_IMM_PSEUDO 0x200000001 /// /// This is to allow rematerialization of a value instead of spilling. It is /// supposed to be done after register coalescer to allow it to do its job and /// before actual register allocation to allow rematerialization. /// /// Right now the pass only handles 64 bit SGPRs with immediate initializers, /// although the same shall be possible with other register classes and /// instructions if necessary. /// //===----------------------------------------------------------------------===// #include "AMDGPU.h" #include "GCNSubtarget.h" #include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "llvm/CodeGen/LiveIntervals.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/InitializePasses.h" usingnamespacellvm; #define DEBUG_TYPE … namespace { class GCNPreRAOptimizations : public MachineFunctionPass { … }; } // End anonymous namespace. INITIALIZE_PASS_BEGIN(GCNPreRAOptimizations, DEBUG_TYPE, "AMDGPU Pre-RA optimizations", false, false) INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass) INITIALIZE_PASS_END(GCNPreRAOptimizations, DEBUG_TYPE, "Pre-RA optimizations", false, false) char GCNPreRAOptimizations::ID = …; char &llvm::GCNPreRAOptimizationsID = …; FunctionPass *llvm::createGCNPreRAOptimizationsPass() { … } bool GCNPreRAOptimizations::processReg(Register Reg) { … } bool GCNPreRAOptimizations::runOnMachineFunction(MachineFunction &MF) { … }