llvm/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp

//===- SIMachineFunctionInfo.cpp - SI Machine Function Info ---------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//

#include "SIMachineFunctionInfo.h"
#include "AMDGPUSubtarget.h"
#include "GCNSubtarget.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "SIRegisterInfo.h"
#include "Utils/AMDGPUBaseInfo.h"
#include "llvm/CodeGen/LiveIntervals.h"
#include "llvm/CodeGen/MIRParser/MIParser.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/IR/DiagnosticInfo.h"
#include "llvm/IR/Function.h"
#include <cassert>
#include <optional>
#include <vector>

enum { … };

usingnamespacellvm;

const GCNTargetMachine &getTM(const GCNSubtarget *STI) { … }

SIMachineFunctionInfo::SIMachineFunctionInfo(const Function &F,
                                             const GCNSubtarget *STI)
    : … { … }

MachineFunctionInfo *SIMachineFunctionInfo::clone(
    BumpPtrAllocator &Allocator, MachineFunction &DestMF,
    const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
    const { … }

void SIMachineFunctionInfo::limitOccupancy(const MachineFunction &MF) { … }

Register SIMachineFunctionInfo::addPrivateSegmentBuffer(
  const SIRegisterInfo &TRI) { … }

Register SIMachineFunctionInfo::addDispatchPtr(const SIRegisterInfo &TRI) { … }

Register SIMachineFunctionInfo::addQueuePtr(const SIRegisterInfo &TRI) { … }

Register SIMachineFunctionInfo::addKernargSegmentPtr(const SIRegisterInfo &TRI) { … }

Register SIMachineFunctionInfo::addDispatchID(const SIRegisterInfo &TRI) { … }

Register SIMachineFunctionInfo::addFlatScratchInit(const SIRegisterInfo &TRI) { … }

Register SIMachineFunctionInfo::addPrivateSegmentSize(const SIRegisterInfo &TRI) { … }

Register SIMachineFunctionInfo::addImplicitBufferPtr(const SIRegisterInfo &TRI) { … }

Register SIMachineFunctionInfo::addLDSKernelId() { … }

SmallVectorImpl<MCRegister> *SIMachineFunctionInfo::addPreloadedKernArg(
    const SIRegisterInfo &TRI, const TargetRegisterClass *RC,
    unsigned AllocSizeDWord, int KernArgIdx, int PaddingSGPRs) { … }

void SIMachineFunctionInfo::allocateWWMSpill(MachineFunction &MF, Register VGPR,
                                             uint64_t Size, Align Alignment) { … }

// Separate out the callee-saved and scratch registers.
void SIMachineFunctionInfo::splitWWMSpillRegisters(
    MachineFunction &MF,
    SmallVectorImpl<std::pair<Register, int>> &CalleeSavedRegs,
    SmallVectorImpl<std::pair<Register, int>> &ScratchRegs) const { … }

bool SIMachineFunctionInfo::isCalleeSavedReg(const MCPhysReg *CSRegs,
                                             MCPhysReg Reg) const { … }

void SIMachineFunctionInfo::shiftSpillPhysVGPRsToLowestRange(
    MachineFunction &MF) { … }

bool SIMachineFunctionInfo::allocateVirtualVGPRForSGPRSpills(
    MachineFunction &MF, int FI, unsigned LaneIndex) { … }

bool SIMachineFunctionInfo::allocatePhysicalVGPRForSGPRSpills(
    MachineFunction &MF, int FI, unsigned LaneIndex, bool IsPrologEpilog) { … }

bool SIMachineFunctionInfo::allocateSGPRSpillToVGPRLane(
    MachineFunction &MF, int FI, bool SpillToPhysVGPRLane,
    bool IsPrologEpilog) { … }

/// Reserve AGPRs or VGPRs to support spilling for FrameIndex \p FI.
/// Either AGPR is spilled to VGPR to vice versa.
/// Returns true if a \p FI can be eliminated completely.
bool SIMachineFunctionInfo::allocateVGPRSpillToAGPR(MachineFunction &MF,
                                                    int FI,
                                                    bool isAGPRtoVGPR) { … }

bool SIMachineFunctionInfo::removeDeadFrameIndices(
    MachineFrameInfo &MFI, bool ResetSGPRSpillStackIDs) { … }

int SIMachineFunctionInfo::getScavengeFI(MachineFrameInfo &MFI,
                                         const SIRegisterInfo &TRI) { … }

MCPhysReg SIMachineFunctionInfo::getNextUserSGPR() const { … }

MCPhysReg SIMachineFunctionInfo::getNextSystemSGPR() const { … }

void SIMachineFunctionInfo::MRI_NoteNewVirtualRegister(Register Reg) { … }

void SIMachineFunctionInfo::MRI_NoteCloneVirtualRegister(Register NewReg,
                                                         Register SrcReg) { … }

Register
SIMachineFunctionInfo::getGITPtrLoReg(const MachineFunction &MF) const { … }

static yaml::StringValue regToString(Register Reg,
                                     const TargetRegisterInfo &TRI) { … }

static std::optional<yaml::SIArgumentInfo>
convertArgumentInfo(const AMDGPUFunctionArgInfo &ArgInfo,
                    const TargetRegisterInfo &TRI) { … }

yaml::SIMachineFunctionInfo::SIMachineFunctionInfo(
    const llvm::SIMachineFunctionInfo &MFI, const TargetRegisterInfo &TRI,
    const llvm::MachineFunction &MF)
    : … { … }

void yaml::SIMachineFunctionInfo::mappingImpl(yaml::IO &YamlIO) { … }

bool SIMachineFunctionInfo::initializeBaseYamlFields(
    const yaml::SIMachineFunctionInfo &YamlMFI, const MachineFunction &MF,
    PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange) { … }

bool SIMachineFunctionInfo::mayUseAGPRs(const Function &F) const { … }

bool SIMachineFunctionInfo::usesAGPRs(const MachineFunction &MF) const { … }